The present invention relates generally to integrated circuit chip testing, and more particularly to method and apparatus for stress testing semiconductor devices.
Historically, in the field of semiconductor technology reliability, stress testing a semiconductor device was done by first dicing a test device from a wafer, mounting it on a carrier, and inserting it in a large temperature chamber with other devices where the Device Under Test (DUT) was wired with power appropriately applied. Typically, DUTs were stressed days and weeks at a time between readouts. For testing, the DUTs were removed and placed on a tester, one at a time.
Progress has brought the state of the art to the point where devices are typically stressed and tested on the wafer using relatively simple test equipment associated with a wafer prober. Stressing is typically done at much higher conditions such that each device is stressed for a few minutes to a few hours and readouts are taken either continuously while the device is being stressed or at least frequently throughout the stress process. This scenario has dictated that only one device at a time on a wafer is stressed. Again, using relatively simple testers that are currently available for wafer-level testing, only a few devices (usually 1 DUT but sometimes as many as 2-4 DUTs) can be stressed and tested. Due to the relative small number of devices being stressed and tested per chip, the amount of data being collected was too small to characterize any real statistical variation across the DUTs.
In recent years, multiple probe heads have become available and, in principle, allow between 2-16 chips to be measured at a time. Multiple probe heads, however, are not an optimal solution to the problems described above, because of their cost, their set-up time, and their relatively poor performance at least for anything greater than about 4 probe heads. Consequently, multiple probe heads have not experienced large scale acceptance. Thus, only one or two DUTs per chip of a particular mechanism configuration are stressed tested.
Negative Bias Temperature Instability (NBTI) has changed the testing process. NBTI has become a very important failure testing mechanism for CMOS PFET transistors as scaling has continued. The understanding of the mechanism has been clouded by rapid relaxation which takes place after stress is removed and by the fact that as devices become narrower the variation in shift rapidly increases, even when the mean shift is relatively well-behaved. Recently, circuitry was designed which allows measurements for relaxation times as short as 10-100 nsec. for a single deice using typical test equipment. (See for example, commonly-owned U.S. patent application Ser. No. 12/061,077. These methods, however, leave the variation across DUTs unresolved. See U.S. Pat. No. 7,111,260 to Visweswariah, of common assignee, and a paper entitled “First-order incremental block-based statistical timing analysis”, by C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, published in the Design Automation Conference (DAC), San Diego, Calif., pages 331-336, June 2004.
When testing, the ability to parallel stress all the DUTs on a given chip (to keep the stress time short), and then accommodate the testing of individual DUTs on that chip while keeping the other devices on that chip under stress to avoid returning to a state of relaxation is desirable.